1. Field of the Invention
This invention relates to a semiconductor device including both a static random access memory (SRAM) and a dynamic random access memory (DRAM).
2. Description of Related Art
A semiconductor device comprising a semiconductor substrate both a SRAM and a DRAM are formed on is well known (for example, see Japanese Unexamined Patent Publication No. 10-041409). High-speed memory access can be obtained with the SRAM and large capacity with small area can be provided with the DRAM. FIG. 8 shows a general circuit configuration of a SRAM cell, which is formed to like this semiconductor device.
As shown in FIG. 8, the SRAM cell generally consists of six transistors. This SRAM cell has a latch circuit 89. The latch circuit 89 includes NMOS transistors 81, 82 and PMOS transistors 83, 84. Further, the SRAM cell includes transfer transistors 85, 86. The transfer transistors 85, 86 transfer data stored in the latch circuit 89 to bit lines BL and /BL.
In the SRAM cell formed as described above, threshold variation of transistors 81-86 becomes a great factor of malfunction according to progress in manufacturing miniaturization. Furthermore, because of lower control voltage for electric power saving, stability of operation gets worse. As a result, there is a problem that yield of manufacturing process becomes lower when the SRAM cell is formed to the semiconductor device. To improve the yield of manufacturing process, new approaches has been researched and developed. For one of the new approaches, a new configuration is applied to the SRAM cell as to obtain high stability even in low-voltage condition (for example, that is shown in “Approaches to control a SRAM variation for LSI are proposed in a stream”, Nikkei electronics, 2006.7, Vol. 17, p. 55-62).
On the other hand, semiconductor device, which the DRAM is formed on, has a sense amplifier. As shown in FIG. 9, the sense amplifier of the DRAM comprises NMOS transistors 91, 92, PMOS transistors 93, 94, and transfer transistors 95, 96. A bit line BL and a complemental bit line /BL of the DRAM cell are connected to nodes n7, n8 in FIG. 9. A potential difference between the bit lines BL, /BL is amplified by the NMOS transistors 91, 92 and the PMOS transistors 93, 94. The NMOS transistors 91, 92 and the PMOS transistors 93, 94 are electrically connected each other like as the latch circuit 89. Data based on the amplified potential difference is transferred to a data bus Bus and /Bus by the transfer transistors 95, 96.
Comparing FIG. 8 with FIG. 9, it can be seen that the NMOS transistors 91, 92 of the sense amplifier correspond to the transistors 81, 82 of the SRAM cell. The PMOS transistors 93, 94 of the sense amplifier correspond to the transistors 83, 84 of the SRAM cell. The transfer transistors 95, 96 of the sense amplifier correspond to the transistors 85, 86 of the SRAM. A circuit 99 (hereinafter, it is called as a latch circuit 99) amplifying the potential difference between a pair of bit lines BL and /BL corresponds to the latch circuit 89 of the SRAM. This is, the sense amplifier of the DRAM has about the same configuration of the SRAM cell.
As described above, when a circuit configuration of the SRAM cell is changed as to save electric power and rein in the negative effect of manufacturing variation, for the semiconductor device including both the SRAM and the DRAM, a configuration of the SRAM cell does not correspond to the sense amplifier of the DRAM. Hence, a tuning window of the SRAM cell does not correspond to the sense amplifier of the DRAM. The tuning window means manufacturing condition in which minimum manufacturing variation can be obtained. When the semiconductor device is manufactured with the tuning window of the SRAM cell, the sense amplifier of the DRAM tends to have a defect. As described above, for the semiconductor device including both the DRAM and the SRAM, when electric power saving is aimed, mass productivity cannot be obtained.